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InsemOct 20222019 patternBE E&TC

VLSI Design & Technology SPPU Insem Question Paper Oct 2022

All 4 questions from this SPPU insem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Insem
Session
Oct 2022
Max. marks
30
Time
1 Hour

Printed for: B.E. (E & TC) (Semester - VII)

Instructions to the candidates

  1. Attempt Q. No. 1 or Q. No. 2 and Q. No. 3 or Q. No. 4.
  2. Neat diagrams must be drawn wherever necessary.
  3. Figures to the right indicate full marks.
  4. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      What is meant by concurrent and sequential statements in VHDL? Describe with two examples of each.

      Also asked:Aug 2025 ·Sep 2024

      [5]
    2. b)

      What is meant by synthesizable and non-synthesizable statement? Give two example of each.

      [5]
    3. c)

      Write VHDL code for 4:1 Mux using behavioral modeling style.

      Also asked:Aug 2025 ·Sep 2024 ·Sep 2023

      [5]

  2. Q2

    1. a)

      Write VHDL Code for full adder and its test bench.

      Also asked:Aug 2025

      [10]
    2. b)

      Explain in brief different modeling styles supported by VHDL.

      Also asked:Sep 2023

      [5]

  3. Q3

    1. a)

      What is Clock Skew? What are techniques to minimize it?

      Also asked:Aug 2025

      [5]
    2. b)

      Draw state diagram and write VHDL code and its test bench for sequence detector 101.

      Also asked:Sep 2024

      [10]

  4. Q4

    1. a)

      What is meant by Meta-stability? Explain any one solution in detail.

      [5]
    2. b)

      Explain clock Distribution Techniques in detail.

      [5]
    3. c)

      This part has equations that don’t show as text. Open the PDF to read it.

      [5]