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EndsemMay 20232019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper May 2023

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
May 2023
Max. marks
70
Time
2½ Hours
Semester
VII
Paper code
[6004]-548

Printed for: B.E. (Electronics & Telecommunication Engg.)

Instructions to the candidates

  1. Neat diagrams must be drawn wherever necessary.
  2. Figures to the right indicate full marks.
  3. Use of electronic pocket calculator is allowed.
  4. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Compare CPLD and FPGA on the basis of features, specifications and applications.

      [6]
    2. b)

      Explain in brief classification of PLDs.

      [6]
    3. c)

      Explain various stages of Synthesis in FPGA with suitable diagram.

      [6]

  2. Q2

    1. a)

      Draw and explain the architecture of FPGA. Explain CLB in detail.

      [10]
    2. b)

      Explain Clock Management Techniques in FPGA.

      [8]

  3. Q3

    1. a)

      Design CMOS logic for Y = AB + CD. Calculate W/L ratio for NMOS and PMOS area needed on chip. Find the total area.

      Also asked:Nov 2024 ·Nov 2023

      [9]
    2. b)

      Discuss need for transmission gate. Draw 4 : 1 Mux using TG.

      Also asked:Nov 2024

      [8]

  4. Q4

    1. a)

      Draw CMOS logic for 2 input NAND gate. Explain its working and draw its stick diagram.

      [9]
    2. b)

      Explain the working of CMOS inverter with the help of Voltage Transfer curve.

      [8]

  5. Q5

    1. a)

      Draw and explain ASIC design flow.

      Also asked:May 2025 ·Nov 2024

      [6]
    2. b)

      Discuss Lambda rules with diagram? (Any 6 rules)

      [6]
    3. c)

      What is stick diagram? Draw Stick diagram of CMOS Inverter. 2

      [6]

  6. Q6

    1. Write short note on :

      [18]
    2. a)

      Antenna Effect.

    3. b)

      Crosstalk.

    4. c)

      Electro migration.

  7. Q7

    1. a)

      Explain need of Design for Testability.

      Also asked:Nov 2025 ·May 2024

      [8]
    2. b)

      Explain Stack at Fault models in brief.

      [9]

  8. Q8

    1. a)

      Write short note on Built in Self-Test.

      [8]
    2. b)

      Write short note on Boundary Scan Method for testing. 

      [9]