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EndsemNov 20232019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper Nov 2023

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
Nov 2023
Max. marks
70
Time
2½ Hours
Semester
VII
Paper code
[6181]-176

Printed for: B.E. (Electronics & Telecommunication Engineering)

Instructions to the candidates

  1. Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
  2. Neat diagrams must be drawn wherever necessary.
  3. Figures to the right indicate full marks.
  4. Use of electronic pocket calculator is allowed.
  5. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Distinguish between FPGA and CPLD.

      [6]
    2. b)

      Explain with diagram SRAM and Anti-fuse programming techniques used in FPGA?

      [6]
    3. c)

      Write short note on VLSI Design flow with respect to PLDs.

      Also asked:Nov 2025 ·May 2025 ·May 2024 ·Sep 2023

      [6]

  2. Q2

    1. a)

      Write short note on CPLD.

      [6]
    2. b)

      Explain synthesis and simulation tools in brief.

      Also asked:Nov 2022

      [6]
    3. c)

      Give typical features and specifications of FPGA.

      [6]

  3. Q3

    1. a)

      Draw and explain CMOS Inverter transfer characteristics with all regions in detail.

      Also asked:Nov 2025 ·May 2025

      [7]
    2. b)

      Draw CMOS logic for Y = AB+ CD E + . Calculate W/L ratio for NMOS and PMOS & area needed on the chip.

      Also asked:Nov 2024 ·May 2023

      [10]

  4. Q4

    1. Write short note on:

    2. a)

      Body effect.

      [4]
    3. b)

      Channel length modulation.

      [4]
    4. c)

      Draw NAND, NOR, AND, OR gates using CMOS. 2

      [9]

  5. Q5

    1. a)

      Explain Antenna effect.

      [5]
    2. b)

      Explain Electro migration effect in detail.

      [5]
    3. c)

      Draw stick diagram of CMOS inverter, 2 input NAND and NOR gates.

      Also asked:Nov 2025 ·May 2024

      [8]

  6. Q6

    1. a)

      Explain LAMBDA rules used for CMOS layout design.

      Also asked:Nov 2025 ·May 2025 ·Nov 2024 ·May 2024 ·Nov 2022

      [6]
    2. b)

      Write short note on Drain punch through.

      [6]
    3. c)

      Write SPICE code for CMOS invertor for AC analysis.

      Also asked:May 2025 ·Nov 2024

      [6]

  7. Q7

    1. a)

      Write short note need of design for Testability & Adhoc DFT techniques.

      [8]
    2. b)

      Explain stuck at fault models with suitable examples.

      [9]

  8. Q8

    1. a)

      Write short note on BIST with block diagram.

      [8]
    2. b)

      This part has equations that don’t show as text. Open the PDF to read it.

      [9]