VLSI Design SPPU Endsem Question Paper May 2025
All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.
- Subject code
- 404182
- Pattern
- 2019 pattern
- Exam
- Endsem
- Session
- May 2025
- Max. marks
- 70
- Time
- 2½ Hours
- Semester
- VII
- Paper code
- [6404]-125
Printed for: B.E. (Electronics & Telecommunication Engineering)
Instructions to the candidates
- Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
- Neat diagrams must be drawn wherever necessary.
- Figures to the right indicate full marks.
- Use of electronic pocket calculator is allowed.
- Assume suitable data, if necessary.
Questions
Q1
- a)[8]
Compare CPLD with FPGA.
- b)[9]
Draw the block diagram of FPGA and explain it in brief.
OR- a)
Q2
- a)[8]
- b)[9]
Draw the block diagram of CPLD and explain it in brief.
Q3
- a)[8]
What is technology scaling? Explain any one type of scaling with its effect at least 4 parameters.
- b)[10]
Explain the working of a transmission gate and implement a circuit of 4:1 MUX using transmission gate.
OR- a)
Q4
- a)[6]
- b)[12]
Explain : Channel Length Modulation, Body Effect, Velocity saturation.
Q5
- a)[6]
- b)[6]
Explain DC and transient analysis using SPICE.
- c)[6]
Explain Antenna Effect in brief.
ORQ6
- a)[6]
- b)[6]
Write short note on Cross talk.
- c)[6]
Q7
- a)[7]
What is DFT? Explain the need for DFT in brief.
- b)[10]
Explain the following terms with respect to testability: i) Fault coverage ii) Fault Models iii) Observability iv) Controllability v) Physical Defects
Also asked:Nov 2024
OR- a)
Q8
- a)[8]
- b)[9]
Explain path sensitizing algorithm in detail.