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InsemOct 20242019 patternTE E&TC

VLSI Design SPPU Insem Question Paper Oct 2024

All 4 questions from this SPPU insem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design questions
Subject code
404182
Pattern
2019 pattern
Exam
Insem
Session
Oct 2024
Max. marks
30
Time
1 Hour
Semester
VII
Paper code
[6361]-91

Printed for: B.E. (E&TC) (Insem)

Instructions to the candidates

  1. Answer Q.1 or Q.2, Q.3 or Q.4.
  2. Figures to the right side indicates full mark.
  3. Draw neat diagram wherever necessary.
  4. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Explain Process Statement in VHDL with suitable examples.

      [5]
    2. b)

      Explain any 2 Concurrent Statement in VHDL with suitable examples.

      Also asked:Aug 2025

      [5]
    3. c)

      Write VHDL code for full adder using behavioral modeling style.

      [5]

  2. Q2

    1. a)

      Write VHDL Code for Arithmetic logic Unit and its test bench.

      [10]
    2. b)

      Explain in brief different WAIT statements supported by VHDL.

      [5]

  3. Q3

    1. a)

      What is Clock Jitter? What are sources of it?

      [5]
    2. b)

      Draw state diagram and write VHDL code and its test bench for sequence detector 111.

      [10]

  4. Q4

    1. a)

      Why should supply and ground bounce be taken care? How are these minimized?

      [5]
    2. b)

      What is Setup time and Hold Time? Explain Meta-stability in detail.

      [5]
    3. c)

      Explain Interconnect routing Techniques. 

      [5]