Skip to content
InsemAug 20252019 patternBE E&TC

VLSI Design & Technology SPPU Insem Question Paper Aug 2025

All 4 questions from this SPPU insem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Insem
Session
Aug 2025
Max. marks
30
Time
1 Hour
Semester
VII
Paper code
[6580]-594

Printed for: B.E. (E & TC) (Insem.)

Instructions to the candidates

  1. Answer Q.l or Q.2, Q.3 or Q.4.
  2. Neat diagrams must be drawn whenever necessary.
  3. Figures to the right indicate full marks.
  4. Assume any missing data if necessary.

Questions

  1. Q1

    1. a)

      Write VHDL Code and its test bench of full adder.

      Also asked:Oct 2022

      [8]
    2. b)

      What is meant by concurrent and sequential statements in VHDL? Describe with examples.

      Also asked:Sep 2024 ·Oct 2022

      [7]

  2. Q2

    1. a)

      Explain in detail digital design flow.

      [8]
    2. b)

      Write VHDL code for 4:1 Mux using behavioral modeling style. Also write it test bench code.

      Also asked:Sep 2024 ·Sep 2023 ·Oct 2022

      [7]

  3. Q3

    1. a)

      Differentiate following: i) Mealy and Moore Machine ii) Fan In and Fan out

      [8]
    2. b)

      What is Clock Skew? What are techniques to minimize it?

      Also asked:Oct 2022

      [7]

  4. Q4

    1. a)

      Write short note on: i) Metastability ii) Noise Margin

      [8]
    2. b)

      What are different signal integrity issues? How to minimize it. 

      Also asked:Sep 2023

      [7]