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EndsemNov 20242019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper Nov 2024

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
Nov 2024
Max. marks
70
Time
2½ Hour
Semester
VII
Paper code
[6354]-529

Printed for: B.E. (Electronics & Telecommunication Engineering)

Instructions to the candidates

  1. Neat diagrams must be drawn wherever necessary.
  2. Figures to the right indicate full marks.
  3. Use of electronic pocket calculator is allowed.
  4. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Write short note on PLDs and explain each device involved in its classification in brief.

      [8]
    2. b)

      Draw the block diagram of CPLD. Explain the following blocks with respect to CPLD : i) Macrocell ii) Product term Allocator:

      [9]

  2. Q2

    1. a)

      Draw block diagram of FPGA. Explain FPGA with respect to the following points: i) Configurable Logic Blocks ii) Programing Techniques

      [9]
    2. b)

      Compare FPGA with CPLD.

      [8]

  3. Q3

    1. a)

      Explain any two Non- Ideal Transistor I-V Effects.

      [8]
    2. b)

      Draw CMOS logic for Y=AB + C (D+E). Calculate W/L ratio for NMOS and PMOS as well as area needed on the chip. 2

      Also asked:Nov 2023 ·May 2023

      [10]

  4. Q4

    1. a)

      A CMOS logic is operating at 10 MHz and 3 V with the load of 100 pF. The static power dissipation is 100uW. Calculate the total power dissipation if the frequency is increased to 100 MHz.

      [6]
    2. b)

      Discuss need for transmission gate. Draw 4:1 Mux using TG.

      Also asked:May 2023

      [6]
    3. c)

      Draw 2 input AND and OR gate using CMOS.

      [6]

  5. Q5

    1. a)

      Explain ASIC Design flow

      Also asked:May 2025 ·May 2023

      [6]
    2. b)

      Explain cell design specification

      [6]
    3. c)

      Draw stick diagram for CMOS Boolean Equation : Y = A+B

      [6]

  6. Q6

    1. a)

      Explain LAMBDA rules used for CMOS layout Design

      Also asked:Nov 2025 ·May 2025 ·May 2024 ·Nov 2023 ·Nov 2022

      [6]
    2. b)

      Write short note on Cross talk

      [6]
    3. c)

      Write SPICE code for CMOS invertor for AC analysis

      Also asked:May 2025 ·Nov 2023

      [6]

  7. Q7

    1. a)

      What are the types of fault? Explain each in brief.

      [7]
    2. b)

      Explain the following terms with respect to testability: i) Fault coverage ii) Fault Models iii) Observability iv) Controllability v) Design for Testability

      Also asked:May 2025

      [10]

  8. Q8

    1. a)

      What is need of BIST? Explain typical BIST in detail.

      Also asked:Nov 2025 ·May 2025 ·May 2024

      [8]
    2. b)

      This part has equations that don’t show as text. Open the PDF to read it.

      [9]