Skip to content
EndsemNov 20222019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper Nov 2022

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
Nov 2022
Max. marks
70
Time
2½ Hours
Semester
VII
Paper code
[5927]-379

Printed for: B.E. (Electronics & Telecommunication Engineering)

Instructions to the candidates

  1. Solve Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
  2. Neat diagrams must be drawn wherever necessary.
  3. Figures to the right indicate full marks.
  4. Use of electronic pocket calculator is allowed.
  5. Assume sitable data, if necessary.

Questions

  1. Q1

    1. a)

      Draw and explain the architecture of CPLD. Explain Macrocell in detail.

      [10]
    2. b)

      What are the technologies supported by FPGA? Explain any two of it detail.

      [8]

  2. Q2

    1. a)

      List and Explain in brief various Simulation and Synthesis Tool.

      Also asked:Nov 2023

      [6]
    2. b)

      Draw and Explain the following for FPGA : i) Logic Cell ii) Programmable Switch Matrix iii) I/O Block

      [12]

  3. Q3

    1. a)

      This part has equations that don’t show as text. Open the PDF to read it.

      [5]
    2. b)

      Draw 2:1 Mux using CMOS as well as TG. Comment on the savings of transistors using TG and CMOS method.

      [12]

  4. Q4

    1. a)

      Define Scaling and Explain any one type of scaling and its effect on at least 4 parameters.

      Also asked:May 2025

      [9]
    2. b)

      Explain the following terms : i) Velocity Saturation ii) Hot Electron Effect 2

      [8]

  5. Q5

    1. a)

      Which Lambda rules are used for CMOS Layout? Give its significance.

      Also asked:Nov 2025 ·May 2025 ·Nov 2024 ·May 2024 ·Nov 2023

      [6]
    2. b)

      Explain the steps involved in fabrication of CMOS transistor with suitable diagram.

      [12]

  6. Q6

    1. Draw the block diagram of half adder and its truth table. Draw it CMOS transistor level circuit. Draw Euler’s Path for both networks. Draw the stick diagram for sum and Carry (outputs) of HALF ADDER.

      [18]

  7. Q7

    1. a)

      Explain different types of faults existing in VLSI chips.

      [8]
    2. b)

      Explain Controllability. Observability and Predictability in testability.

      [9]

  8. Q8

    1. a)

      Explain Path sensitization method.

      [8]
    2. b)

      This part has equations that don’t show as text. Open the PDF to read it.

      [9]