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EndsemMay 20242019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper May 2024

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
May 2024
Max. marks
70
Time
2½ Hours
Semester
VII
Paper code
[6263]-125

Printed for: B.E. (Electronics and Telecommunication)

Instructions to the candidates

  1. Solve Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.
  2. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Draw and explain the architecture of CPCD and compare between CPCD and FPGA.

      [10]
    2. b)

      Write feature of FPGA in detail and write its applications.

      [8]

  2. Q2

    1. a)

      Draw and explain CLB in detail.

      [8]
    2. b)

      Draw and explain PLD design flow.

      Also asked:Nov 2025 ·May 2025 ·Nov 2023 ·Sep 2023

      [10]

  3. Q3

    1. a)

      This part has equations that don’t show as text. Open the PDF to read it.

      [8]
    2. b)

      What are the merits of transmission gate and design 2:1 multiplexer using transmission gate.

      Also asked:Nov 2025

      [9]

  4. Q4

    1. a)

      Write short note on Hot electron effect.

      [6]
    2. b)

      Write short note on Power dissipation.

      [6]
    3. c)

      Write short note on Body effect.

      [5]

  5. Q5

    1. a)

      Explain in detail lambda design rules in CMOS VLSI.

      Also asked:Nov 2025 ·May 2025 ·Nov 2024 ·Nov 2023 ·Nov 2022

      [9]
    2. b)

      Draw stick diagram for invester, NAND and NOR gate. 2

      Also asked:Nov 2025 ·Nov 2023

      [9]

  6. Q6

    1. a)

      Write short note on Electrical Rule Check.

      [6]
    2. b)

      Write short note on Antenna Effect.

      [6]
    3. c)

      Write short note on Cross talk and drain punch.

      [6]

  7. Q7

    1. a)

      What is the need of BIST? Explain typical BIST in detail.

      Also asked:Nov 2025 ·May 2025 ·Nov 2024

      [9]
    2. b)

      Write short note on i) JTAG ii) Boundry scan

      Also asked:Nov 2025

      [8]

  8. Q8

    1. a)

      Explain the need for design for testability? Explain stuck at 0 and stuck at 1 fault with example.

      Also asked:Nov 2025 ·May 2023

      [9]
    2. b)

      This part has equations that don’t show as text. Open the PDF to read it.

      [8]