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EndsemMay 20252019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper May 2025

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
May 2025
Max. marks
70
Time
2½ Hours
Semester
VII
Paper code
[6404]-125

Printed for: B.E. (Electronics & Telecommunication Engineering)

Instructions to the candidates

  1. Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
  2. Neat diagrams must be drawn wherever necessary.
  3. Figures to the right indicate full marks.
  4. Use of electronic pocket calculator is allowed.
  5. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Compare CPLD with FPGA.

      [8]
    2. b)

      Draw the block diagram of FPGA and explain it in brief.

      [9]

  2. Q2

    1. a)

      Explain in brief PLD Design flow.

      Also asked:Nov 2025 ·May 2024 ·Nov 2023 ·Sep 2023

      [8]
    2. b)

      Draw the block diagram of CPLD and explain it in brief.

      [9]

  3. Q3

    1. a)

      What is technology scaling? Explain any one type of scaling with its effect at least 4 parameters.

      Also asked:Nov 2022

      [8]
    2. b)

      Explain the working of a transmission gate and implement a circuit of 4:1 MUX using transmission gate.

      [10]

  4. Q4

    1. a)

      Draw and explain CMOS inverter transfer characteristics.

      Also asked:Nov 2025 ·Nov 2023

      [6]
    2. b)

      Explain : Channel Length Modulation, Body Effect, Velocity saturation.

      [12]

  5. Q5

    1. a)

      Explain ASIC Design flow.

      Also asked:Nov 2024 ·May 2023

      [6]
    2. b)

      Explain DC and transient analysis using SPICE.

      [6]
    3. c)

      Explain Antenna Effect in brief.

      [6]

  6. Q6

    1. a)

      Explain LAMBDA rules used for CMOS layout design.

      Also asked:Nov 2025 ·Nov 2024 ·May 2024 ·Nov 2023 ·Nov 2022

      [6]
    2. b)

      Write short note on Cross talk.

      [6]
    3. c)

      Write SPICE code for CMOS invertor for AC analysis. 2

      Also asked:Nov 2024 ·Nov 2023

      [6]

  7. Q7

    1. a)

      What is DFT? Explain the need for DFT in brief.

      [7]
    2. b)

      Explain the following terms with respect to testability: i) Fault coverage ii) Fault Models iii) Observability iv) Controllability v) Physical Defects

      Also asked:Nov 2024

      [10]

  8. Q8

    1. a)

      What is need of BIST? Explain typical BIST in detail.

      Also asked:Nov 2025 ·Nov 2024 ·May 2024

      [8]
    2. b)

      Explain path sensitizing algorithm in detail. 

      [9]