Skip to content
EndsemNov 20252019 patternBE E&TC

VLSI Design & Technology SPPU Endsem Question Paper Nov 2025

All 8 questions from this SPPU endsem paper, as printed. Read them here or open the PDF.

Open the PDFMost repeated VLSI Design & Technology questions
Subject code
404182
Pattern
2019 pattern
Exam
Endsem
Session
Nov 2025
Max. marks
70
Time
2½ Hours
Semester
VII
Paper code
[6584]-135

Printed for: B.E. (Electronics and Telecommunication Engineering)

Instructions to the candidates

  1. Solve Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.
  2. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Write the features of CPLD in detail and give it's applications.

      [8]
    2. b)

      Draw and explain the architecture of FPGA & compare between CPLD and FPGA.

      [10]

  2. Q2

    1. a)

      Draw and explain macrocell in detail.

      [8]
    2. b)

      Draw and explain PLD design flow.

      Also asked:May 2025 ·May 2024 ·Nov 2023 ·Sep 2023

      [10]

  3. Q3

    1. a)

      Draw and explain CMOS Inverter schematic and it's voltage transfer characteristics.

      Also asked:May 2025 ·Nov 2023

      [9]
    2. b)

      What are the merits of Transmission gate? Design 2:1 multiplexer using transmission gate.

      Also asked:May 2024

      [8]

  4. Q4

    1. a)

      Write short note on channel legth modulation.

      [6]
    2. b)

      Write short note on Device siziry.

      [6]
    3. c)

      Write short note on velocity saturation.

      [5]

  5. Q5

    1. a)

      What is DRC? Explain in detail rules in CMOS VLSI design?

      Also asked:May 2025 ·Nov 2024 ·May 2024 ·Nov 2023 ·Nov 2022

      [9]
    2. b)

      Draw stick diagram for Inverter, NAND and NOR gate.

      Also asked:May 2024 ·Nov 2023

      [9]

  6. Q6

    1. a)

      Write short note on Design issues like Antenna Effect.

      [6]
    2. b)

      Write short note on SPICE simulation.

      [6]
    3. c)

      Write short note on Layout Vs schematic.

      [6]

  7. Q7

    1. a)

      Explain the need for Design for Testability? Explain stuck-at-0 and stuck- at-1 faults with example.

      Also asked:May 2024 ·May 2023

      [9]
    2. b)

      Write short note on i) JTAG ii) Boundary scan

      Also asked:May 2024

      [8]

  8. Q8

    1. a)

      What is the need of BIST? Explain typical BIST in detail.

      Also asked:May 2025 ·Nov 2024 ·May 2024

      [9]
    2. b)

      Draw the TAP controller state diagram and explain. 

      [8]