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InsemOct 20242019 patternSE E&TC

Digital Circuits SPPU Insem Question Paper Oct 2024

This 2019-pattern Digital Circuits paper is listed under Digital Electronics. All 6 questions are below, as printed.

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Subject code
204182
Pattern
2019 pattern
Exam
Insem
Session
Oct 2024
Max. marks
30
Time
1 Hour
Semester
III
Paper code
[6359]-513

Printed for: S.E. ( ELECTRONICS / E&TC/Electronics & Computer ( Electronics

Instructions to the candidates

  1. Answer Q1 or Q2, Q3 or Q4, Q5 or Q6.
  2. Figures to the right indicates full marks.
  3. Neat diagram must be drawn wherever necessary.
  4. Use of non-programmable calculator is allowed.
  5. Assume suitable data, if necessary.

Questions

  1. Q1

    1. a)

      Explain the following characteristics of digital IC’s: i) Figure of Merit ii) Propagation delay. iii) V IH and V OH

      [6]
    2. b)

      Draw and explain the working of CMOS Inverter.

      [4]

  2. Q2

    1. a)

      Draw and explain the working of 2- input TTL NAND gate. List advantages of Totem Pole.

      [6]
    2. b)

      Explain the following characteristics of digital IC’s: i) Noise Margin ii) Fan out and Fan in

      [4]

  3. Q3

    1. a)

      Design full adder using logic gates.

      [4]
    2. b)

      This part has equations that don’t show as text. Open the PDF to read it.

      [6]

  4. Q4

    1. a)

      Design 3-bit Gray code to Binary converter.

      Also asked:May 2024

      [6]
    2. b)

      Design full subtractor using logic gates.

      [4]

  5. Q5

    1. a)

      Minimize the following function using K-map and implement it using only NAND gates. F(P,Q,R,S) =  m(4,5,6,7,8,12) + d(l,2,3,9,l1,14)

      [6]
    2. b)

      Compare TTL and CMOS logic families.

      [4]

  6. Q6

    1. a)

      Explain the current parameters in TTL logic.

      [4]
    2. b)

      This part has equations that don’t show as text. Open the PDF to read it.

      [6]