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EndsemMay 20252019 patternSE E&TC

Digital Circuits SPPU Endsem Question Paper May 2025

This 2019-pattern Digital Circuits paper is listed under Digital Electronics. All 8 questions are below, as printed.

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Subject code
204182
Pattern
2019 pattern
Exam
Endsem
Session
May 2025
Max. marks
70
Time
2½ Hours
Semester
III
Paper code
[6402]-23

Printed for: S.E. (Electronics & Computer) (Electronics/E&TC)

Instructions to the candidates

  1. Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8 .
  2. Neat diagrams must be drawn wherever necessary.
  3. Figures to the right indicate full marks.

Questions

  1. Q1

    1. a)

      Design a full adder using 2 half adders.

      [7]
    2. b)

      Design and implement one bit comparator.

      Also asked:Dec 2025 ·May 2024

      [5]
    3. c)

      Design 16:1 multiplexer using two 8:1 multiplexer.

      [5]

  2. Q2

    1. a)

      Design and explain 1:4 DEMUX with block diagram, truth-table, equation and logic diagram.

      [7]
    2. b)

      Implement the full subtractor using a 1:8 demultiplexer.

      [5]
    3. c)

      Draw and explain the look-ahead carry generator.

      Also asked:Dec 2025

      [5]

  3. Q3

    1. a)

      Design a sequence generator using T FFs for sequence 1101.

      [8]
    2. b)

      Distinguish between synchronous counter and asynchronous counter.

      [5]
    3. c)

      Explain with diagram the working of D type Flip-flop. Give its truth table.

      [5]

  4. Q4

    1. a)

      Draw and explain 3 bit asynchronous counter using JK FF.

      Also asked:May 2024

      [8]
    2. b)

      Design a 3 bit twisted ring counter. Draw logic diagram.

      [5]
    3. c)

      Compare Moore and Mealy machines.

      Also asked:May 2024

      [5]

  5. Q5

    1. a)

      What do you mean by excitation table of flip flop? Write the excitation table of i) D flip flop ii) J-K flip flop

      [9]
    2. b)

      Explain : i) State Table ii) State Diagram iii) State Assignment iv) ASM chart

      [8]

  6. Q6

    1. a)

      Design a sequence detector to detect a sequence 1101 using D FF (Use Moore machine)

      [9]
    2. b)

      Explain in short: i) Moore Machine ii) Mealy Machine

      Also asked:May 2024

      [8]

  7. Q7

    1. a)

      Explain block diagram of FPGA with its basic characteristics.

      [8]
    2. b)

      Write short notes on memories.

      [10]

  8. Q8

    1. a)

      This part has equations that don’t show as text. Open the PDF to read it.

      [8]
    2. b)

      Describe with neat diagram AND-OR structure of PLA and PAL. 

      [10]