Digital Electronics and Logic Design (DELD) SPPU Insem Question Paper Oct 2024

Questions

1. Q1

   1. a)

      Solve the following equation using K-map minimization techniques. Also draw the diagram using basic gates F(A,B,C,D)=  m (2,7,8,10,11,13,15)

      [5]
   2. b)

      Minimize the function in POS form and also draw the diagram F(A,B,C,D)=  M(0,1,3,5,6,7,9,10,15)

      Also asked:Nov 2025

      [5]
   3. c)

      How will you implement full adder using half adder? Explain the circuit diagram.

      [5]
   OR

2. Q2

   1. a)

      Represent the following decimal numbers in i) Sign magnitude form ii) Sign 1’s complement form iii) Sign 2’s complement form 1) +14 2) +27 3) –17 4) +45

      Also asked:Nov 2025

      [5]
   2. b)

      Minimize the following logic function using K-map and realize using logic gates. Draw the diagram F(A,B,C,D)=  m(1,3,7,11,15)+d(0,2,5)

      [5]
   3. c)

      Simplify logic equation using Quine Mc Cluskey minimization Technique Y(A,B,C,D)=  m(0,1,3,7,8,9,11,15) 2

      Also asked:Nov 2025

      [5]

3. Q3

   1. a)

      Design and Implement 4 bit Binary to Gray code converter using logic gate.

      Also asked:Nov 2025

      [5]
   2. b)

      Design single digit BCD adder using 4 Bit binary adder IC 7483.

      Also asked:Nov 2025

      [5]
   3. c)

      Implement the expression using a 8:1 multiplexer F(A,B,C,D)=  m(0,2,3,6,8,9,12,14)

      [5]
   OR

4. Q4

   1. a)

      Write a short note on look ahead carry generator also explain its importance.

      [5]
   2. b)

      Design 2-bit magnitude comparator using logic gates.

      Also asked:Nov 2025

      [5]
   3. c)

      Design 3 bit parity generator circuit using odd parity bit. 

      [5]