Digital Electronics and Logic Design (DELD) SPPU Insem Question Paper Nov 2025
All 4 questions from this SPPU insem paper, as printed. Read them here or open the PDF.
- Subject code
- 210245
- Pattern
- 2019 pattern
- Exam
- Insem
- Session
- Nov 2025
- Max. marks
- 30
- Time
- 1 Hour
- Semester
- III
- Paper code
- [6578]-23
Printed for: S.E. (Computer Engineering) (Insem.)
Instructions to the candidates
- Attempt Q1 or Q2, Q3 or Q4.
- Neat diagram must be drawn wherever necessary.
- Assume suitable data if necessary.
Questions
Q1
- a)[5]
Minimize the function in SOP form and also draw the diagram f(A,B,C,D) = m (0,2,3,5,6,9,11,15) + d(1,13,14)
Also asked:Oct 2024
- b)[5]
Simplify logic equation using Quine Mc Cluskey minimization Technique. Y(A,B,C,D) = m (0,1,3,7,8,9,11,15)
Also asked:Oct 2024
- c)[5]
Obtain the minimal POS expression for the following and also draw the diagram using logic gates. F( A,B,C,D) = M( 0,1,2,4,5,6,9,11,12,13,14,15)
OR- a)
Q2
- a)[5]
Write application of Gray Code. Design 3 bit Binary to Gray code converter
Also asked:Oct 2024
- b)[5]
Minimize the function in SOP form f(A,B,C,D) = m (0,1,2,3,6,9,10,13,15) Also draw the diagram
Also asked:Oct 2024
- c)
Write in i) sign magnitude form ii) l’s complement form iii) 2’s complement form
Also asked:Oct 2024
- a)[5]
This part has equations that don’t show as text. Open the PDF to read it.
- a)
Q3
- a)[5]
Design 3 bit BCD to Ex-3 code converter. Draw the diagram.
- b)[5]
Design single digit BCD adder using 4 bit binary adder IC 7483.
Also asked:Oct 2024
- c)[5]
Implement full adder using two 4:1 multiplexer and OR gate
OR- a)
Q4
- a)[5]
Design 2 bit magnitude comparator using gates
Also asked:Oct 2024
- b)[5]
This part has equations that don’t show as text. Open the PDF to read it.
- c)[5]
This part has equations that don’t show as text. Open the PDF to read it.
- a)